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Espressif Systems /ESP32-S3 /SENS /SAR_COCPU_DEBUG

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Interpret as SAR_COCPU_DEBUG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SAR_COCPU_PC0 (SAR_COCPU_MEM_VLD)SAR_COCPU_MEM_VLD 0 (SAR_COCPU_MEM_RDY)SAR_COCPU_MEM_RDY 0SAR_COCPU_MEM_WEN 0SAR_COCPU_MEM_ADDR

Description

Ulp-riscv debug signal

Fields

SAR_COCPU_PC

cocpu Program counter
SAR_COCPU_MEM_VLD

cocpu mem valid output
SAR_COCPU_MEM_RDY

cocpu mem ready input
SAR_COCPU_MEM_WEN

cocpu mem write enable output
SAR_COCPU_MEM_ADDR

cocpu mem address output

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data